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| 50 mhz to 525 mhz quadrature demodulator with fractional-n pll and vco data sheet adrf6806 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010C2012 analog devices, inc. all rights reserved. features iq demodulator with integrated fractional-n pll lo frequency range: 50 mhz to 525 mhz for the following specifications (lpen = 0)/(lpen = 1): input p1db: 12.2 dbm/10.6 dbm input ip3: 28.5 dbm/25.2 dbm noise figure (dsb): 12.2/11.4 voltage conversion gain: 1 db/4.2 db quadrature demodulation accuracy phase accuracy: <0.5 amplitude accuracy: <0.1 db baseband demodulation: 135 mhz, 3 db bandwidth spi serial interface for pll programming 40-lead, 6 mm 6 mm lfcsp applications qam/qpsk rf/if demodulators cellular w-cdma/cdma/cdma2000 microwave point-to-(multi)point radios broadband wireless and wimax general description the adrf6806 is a high dynamic range iq demodulator with integrated pll and vco. the fractional-n pll/synthesizer generates a frequency in the range of 2.8 ghz to 4.2 ghz. a programmable quadrature divider (divide ratio = 4 to 80) divides the output frequency of the vco down to the required local oscillator (lo) frequency to drive the mixers in quadrature. additionally, an output divider (divide ratio = 4 to 8) generates a divided-down vco signal for external use. the pll reference input is supported from 10 mhz to 160 mhz. the phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. the loop filter output is then applied to an integrated vco. the iq demodulator mixes the differential rf input with the complex lo derived from the quadrature divider. the differential i and q output paths have excellent quadrature accuracy and can handle baseband signaling or complex if up to 120 mhz. a reduced power mode of operation is also provided by programming the serial interface registers to reduce current consumption, with slightly degraded input linearity and output current drive. the adrf6806 is fabricated using an advanced silicon-germanium bicmos process. it is available in a 40-lead, exposed-paddle, rohs-compliant, 6 mm 6 mm lfcsp package. performance is specified over the ?40c to +85c temperature range. functional block diagram mux rset gnd lon lop mux temp sensor gnd decl3 vccrf v cclo buffer buffer qbbn v cclo ? + charge pump 250a, 500a (default), 750a, 1000a prescaler 2 vco ldo 2.5v ldo le clk spi interface data muxout refin adrf6806 34 gnd losel 35 19 qbbp 18 17 16 decl1 40 vtune 39 decl2 vcc2 9 10 5 vcc1 2 vcc1 1 8 6 gnd 7 14 gnd 15 13 12 38 gnd 11 37 36 gnd 31 ibbn ibbp 32 33 28 gnd 27 rfin 26 rfip 25 gnd 24 vocm 23 vccbb 22 gnd gnd 21 20 29 30 phase frequency detector third-order fractional interpolator fraction reg modulus integer reg n counter gnd 4 cpout 3 2 2 4 divider 2 to 40 vco core 09335-001 buffer ctrl quad 2 div 4, 6, 8 figure 1.
adrf6806 data sheet rev. b | page 2 of 36 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? timing characteristics ................................................................ 5 ? absolute maximum ratings............................................................ 6 ? esd caution.................................................................................. 6 ? pin configuration and function descriptions............................. 7 ? typical performance characteristics ............................................. 9 ? synthesizer/pll .......................................................................... 12 ? complementary cumulative distribution functions (ccdf) ....................................................................................................... 13 ? circuit description......................................................................... 14 ? lo quadrature drive................................................................. 14 ? v-to-i converter......................................................................... 14 ? mixers .......................................................................................... 14 ? emitter follower buffers ........................................................... 14 ? bias circuitry .............................................................................. 14 ? register structure....................................................................... 14 ? lo divider programming......................................................... 21 ? programming example.............................................................. 21 ? applications information .............................................................. 22 ? basic connections...................................................................... 22 ? supply connections ................................................................... 22 ? synthesizer connections ........................................................... 22 ? i/q output connections ........................................................... 23 ? rf input connections ............................................................... 23 ? charge pump/vtune connections ...................................... 23 ? lo select interface ..................................................................... 23 ? external lo interface ................................................................ 23 ? setting the frequency of the pll ............................................. 23 ? register programming............................................................... 23 ? evm measurements .................................................................. 24 ? evaluation board layout and thermal grounding................... 25 ? adrf6806 software .................................................................. 30 ? characterization setups................................................................. 32 ? outline dimensions ....................................................................... 36 ? ordering guide .......................................................................... 36 ? revision history 3/12rev. a to rev. b changes to phase noiseusing 67 khz loop filter parameter, table 1; added phase noiseusing 2.5 khz loop filter parameter, table 1; added pll figure of merit (fom) parameter, table 1 ........................................................................ 4 changes to figure 21 and figure 24 to figure 26....................... 12 changes to figure 34...................................................................... 16 changes to figure 37...................................................................... 18 changes to figure 38...................................................................... 19 changes to figure 39...................................................................... 20 changes to evm measurements section and figure 42, deleted figure 43; renumbered sequentially ........................ 24 changes to figure 43...................................................................... 25 added figure 44.............................................................................. 26 changes to figure 46 and figure 47............................................. 27 changes to table 7.......................................................................... 29 changes to figure 48...................................................................... 30 changes to figure 49...................................................................... 31 6/11rev. sp0 to rev. a data sheet adrf6806 rev. b | page 3 of 36 specifications v s1 (v vccbb and v vccrf ) = 5 v, and v s2 (v vcc1 , v vcc2 , and v vcclo ) = 3.3 v; ambient temperature (t a ) = 25c; f ref = 26 mhz, f lo = 140 mhz, f bb = 4.5 mhz, r load = 450 differential, rf port driven from a 1:2 balun to step up the 50 source impedance to match the 100 differential rf input port impedance, all register and pll settings use the recommended values shown in the register structure section, unless otherwise noted. table 1. parameter test conditions/comments min typ max unit frequency range 50 525 mhz rf input @ 140 mhz rfip, rfin pins input return loss relative to 100 ?11.7 db input p1db lpen = 0 (standard power mode) 12.2 dbm lpen = 1 (low power mode) 10.6 dbm second-order input intercept (iip2) lpen = 0; ?5 dbm each tone >65 dbm lpen = 1; ?5 dbm each tone >60 dbm third-order input intercept (iip3) lpen = 0; ?5 dbm each tone 28.5 dbm lpen = 1; ?5 dbm each tone 25.2 dbm noise figure double sideband from rf to either i or q output; lpen = 0 12.2 db double sideband from rf to either i or q output; lpen = 1 11.4 db with a ?5 dbm interferer 5 mhz away 14 db lo-to-rf leakage at 1lo frequency, 100 termination at the rf port ?70 dbm i/q baseband outputs ibbp, ibbn, qbbp, qbbn pins voltage conversion gain 450 differential load across ibbp, ibbn (or qbbp, qbbn); lpen = 0 1 db 450 differential load across ibbp, ibbn (or qbbp, qbbn); lpen = 1 4.2 db demodulation bandwidth 1 v p-p signal 3 db bandwidth; lpen = 0 170 mhz 1 v p-p signal 3 db bandwidth; lpen = 1 135 mhz quadrature phase error 0.3 degrees i/q amplitude imbalance 0.05 db output dc offset (differential) 8 mv output common-mode reference vocm applied input voltage 1.55 1.65 1.75 v common-mode offset |(v ibbp + v ibbn )/2 ? v vocm |, |(v qbbp + v qbbn )/2 ? v vocm | 25 mv gain flatness any 5 mhz 0.2 db p-p maximum output swing differential 450 load 3 v p-p differential 200 load 2.4 v p-p maximum output current each pin 6 ma p-p lo input/output lop, lon output level (lpen = 0) into a differential 50 load, lo buffer enabled (output frequency = 800 mhz) 1 dbm output level (lpen = 1) into a differential 50 load, lo buffer enabled (output frequency = 800 mhz) ?0.75 dbm input level externally applied 2lo, pll disabled 0 dbm input impedance externally appl ied 2lo, pll disabled 50 lo main divider range vco to mixer, including quadrature divider, see table 5 for supported divider modes 8 80 vco output divider range vco to (lop, lon), see table 6 for supported output divider modes 4 8 vco operating frequency 2800 4200 mhz synthesizer specifications all synthesizer specifications measured with recommended settings provided in figure 33 through figure 40 channel spacing f pfd = 26 mhz 25 khz pll bandwidth can be adjusted with off-chip loop filter component values and r set 67 khz adrf6806 data sheet rev. b | page 4 of 36 parameter test conditions/comments min typ max unit spurs f lo = 140 mhz, f ref = 26 mhz, f pfd = 26 mhz, measured at bb outputs with f bb = 50 mhz reference spurs f ref = 26 mhz, f pfd = 26 mhz ?95 dbc f ref /2 ?106 dbc f ref 2 ?100 dbc f ref 3 ?105 dbc phase noiseusing 67 khz loop filter f lo = 140 mhz, f ref = 26 mhz, f pfd = 26 mhz, measured at bb outputs with f bb = 50 mhz @ 1 khz offset ?117 dbc/hz @ 10 khz offset ?124 dbc/hz @ 100 khz offset ?127 dbc/hz @ 500 khz offset ?146 dbc/hz @ 1 mhz offset ?149 dbc/hz @ 5 mhz offset ?151 dbc/hz @ 10 mhz offset ?153 dbc/hz integrated phase noise 1 khz to 10 mhz integration bandwidth 0.03 rms phase noiseusing 2.5 khz loop filter f lo = 900 mhz, f ref = 26 mhz, f pfd = 26 mhz, measured at bb outputs with f bb = 50 mhz @ 1 khz offset ?95 dbc/hz @ 10 khz offset ?110 dbc/hz @ 100 khz offset ?136 dbc/hz @ 500 khz offset ?149 dbc/hz @ 1 mhz offset ?149.5 dbc/hz @ 5 mhz offset ?151 dbc/hz @ 10 mhz offset ?153 dbc/hz pll figure of merit (fom) measured with f ref = 26 mhz, f pfd = 26 mhz ?215.4 dbc/hz/hz measured with f ref = 104 mhz, f pfd = 26 mhz ?220.9 dbc/hz/hz phase detector frequency 20 26 40 mhz reference characteristics refin, muxout pins refin input frequency usable range 9 160 mhz refin input capacitance 4 pf muxout output level v ol (lock detect output selected) 0.25 v v oh (lock detect output selected) 2.7 v refout duty cycle 50 % charge pump pump current 500 a output compliance range 1 2.8 v logic inputs clk, data, le pins input high voltage, v inh 1.4 3.3 v input low voltage, v inl 0 0.7 v input current, i inh /i inl 0.1 a input capacitance, c in 5 pf power supplies vcc1, vcc2, vcclo, vccbb, vccrf pins voltage range (3.3 v) vcc1, vcc2, vcclo 3.135 3.3 3.465 v voltage range (5 v) vccbb, vccrf 4.75 5 5.25 v supply current (3.3 v) (lpen = 0) normal rx mode 209 ma rx mode with lo buffer enabled 270 ma supply current (5 v) (lpen = 0) normal rx mode 86 ma rx mode with lo buffer enabled 86 ma supply current (3.3 v) (lpen = 1) normal rx mode 205 ma rx mode with lo buffer enabled 258 ma data sheet adrf6806 rev. b | page 5 of 36 parameter test conditions/comments min typ max unit supply current (5 v) (lpen = 1) normal rx mode 75 ma rx mode with lo buffer enabled 75 ma supply current (5 v) power-down mode 10 ma supply current (3.3 v) power-down mode 15 ma timing characteristics v s1 (v vccbb and v vccrf ) = 5 v, and v s2 (v vcc1 , v vcc2 , and v vcclo ) = 3.3 v. table 2. parameter limit at t min to t max (b version) unit test conditions/comments t 1 20 ns min le setup time t 2 10 ns min data to clk setup time t 3 10 ns min data to clk hold time t 4 25 ns min clk high duration t 5 25 ns min clk low duration t 6 10 ns min clk to le setup time t 7 20 ns min le pulse width c loc k data le le db23 (msb) db22 db2 db1 (control bit c2) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 09335-002 figure 2. timing diagram adrf6806 data sheet rev. b | page 6 of 36 absolute maximum ratings table 3. parameter rating supply voltage, vccbb and vccrf (v s1 ) ?0.5 v to +5.5 v supply voltage, vcc1, vcc2, and vcclo (v s2 ) ?0.5 v to +3.6 v digital i/o, clk, data, and le ?0.3 v to +3.6 v rfip and rfin (each pin ac-coupled) 13 dbm ja (exposed paddle soldered down) 30c/w maximum junction temperature 150c operating temperature range ?40c to +85c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution data sheet adrf6806 rev. b | page 7 of 36 pin configuration and fu nction descriptions 1 2 3 30 29 28 4 5 6 7 8 22 23 24 25 26 27 9 10 21 40 39 38 vcclo ibbn losel ibbp gnd 32 33 34 35 36 37 31 20 19 18 12 13 14 15 16 17 11 rfin gnd lon lop decl1 gnd rset vcc1 cpout vcc2 refin decl2 vcc1 third-order sdm vco band current cal/set vco 2800mhz to 2h400mhz phase detector and charge pump quadrature 2 serial port 2 enable vtune programable divider 4 mux prescaler 2 vco ldo 2.5v ldo mux integer fraction 6 6 bleed scale qbbn gnd clk data qbbp vcclo le gnd gnd gnd vocm decl3 gnd vccbb vccrf gnd gnd rfip gnd div 2 to 40 div 4, 6, 8 modulus buffer ctrl div ctrl gnd common- mode level control muxout notes 1. the exposed paddle should be soldered to a low impedance ground plane. 2 div ctrl 09335-003 figure 3. pin configuration table 4. pin function descriptions pin o. mnemonic description 1, 2 vcc1 the 3.3 v power supply for vco and pll. 3 cpout charge pump output pin. connect this pin to vtune through the loop filter. 4, 7, 11, 15, 16, 20, 21, 24, 27, 30, 31, 35 gnd connect these pins to a low impedance ground plane. 5 rset charge pump current. the nominal charge pump current can be set to 250 a, 500 a, 750 a, or 1 ma using db10 and db11 of register 4 and by setting db18 to 0 (internal reference current). in this mode, no external r set is required. if db18 is set to 1, th e four nominal charge pump currents (i nominal ) can be externally tweaked according to the following equation where the resulting value is in units of ohms. 8.37 4.217 ? ? ? ? ? ? ? = nominal cp set i i r 6 refin reference input. nominal input level is 1 v p-p. input range is 9 mhz to 160 mhz. adrf6806 data sheet rev. b | page 8 of 36 pin no. mnemonic description 8 muxout multiplexer output. this output can be programmed to provide the reference output signal or the lock detect signal. the output is selected by programming the appropriate register. 9 decl2 connect a 0.1 f capacitor between this pin and ground. 10 vcc2 the 3.3 v power supply for the 2.5 v ldo. 12 data serial data input. the serial data is loaded msb first with the three lsbs being the control bits. 13 clk serial clock input. this serial clock is used to cloc k in the serial data to the registers. the data is latched into the 24-bit shift register on the clk rising edge. maximum clock frequency is 20 mhz. 14 le load enable. when the le input pin goes high, the da ta stored in the shift registers is loaded into one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word. 17, 34 vcclo the 3.3 v power supply for the lo path blocks. 18, 19 qbbp, qbbn demodulator q-channel differential base band outputs (differential output impedance of 28 ). 22 vccbb the 5 v power supply for the demodulator blocks. 23 vocm baseband common-mode reference input; 1.65 v nominal. it sets the dc common-mode level of the ibbx and qbbx outputs. 25, 26 rfip, rfin differential 100 , internally bi ased rf inputs. these pins must be ac-coupled. 28 vccrf the 5 v power supply for the demodulator blocks. 29 decl3 connect a 2.2 f capacitor between this pin and ground. 32, 33 ibbn, ibbp demodulator i-channel differential ba seband outputs (differential output impedance of 28 ). 36 losel lo select. connect this pin to ground for the simplest operation and to completely control the lo path and input/output direction from the register spi programming. for additional control without register reprogra mming, this input pin can determine whether the lop and lon pins operate as inputs or outputs. lo p and lon become inputs if the losel pin is set low, the ldrv bit of register 5 is set low, and the lxl bit of register 5 is set high. the externally applied lo drive must be at mlo frequency (where m corresponds to the main lo divider setting). lon and lop become outputs when losel is high or if the ldrv bit of register 5 (db3) is set high and the lxl bit of register 5 (db4) low. the output freq uency is controlled by the lo output divider bits in register 7. this pin should not be left floating. 37, 38 lon, lop local oscillator input/output. wh en these pins are used as outp ut pins, a differential frequency divided version of the internal vco is available on these pins. when the internal lo generation is disabled, an external mlo frequency signal can be applied to these pins (where m corresponds to the main divider setting). (different ial input/output impedance of 50 ) 39 vtune vco control voltage input. this pin is driven by the output of the loop filter. the nominal input voltage range on this pin is 1.0 v to 2.8 v. 40 decl1 connect a 10 f capacitor between this pin and grou nd as close to the device as possible because this pin serves as the vco supply and loop filter reference. ep exposed paddle. the exposed paddle should be soldered to a low impedance ground plane. data sheet adrf6806 rev. b | page 9 of 36 typical performance characteristics v s1 = 5 v, v s2 = 3.3 v, t a = 25c, rf input balun loss is de -embedded, unless otherwise noted. lo = 50 mhz to 525 mhz; mini-circuits adtl2-18 balun on rf inputs. 0 2 4 6 8 10 12 14 16 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 conversion gain (db) and input p1db (dbm) lo frequency (mhz) t a = +85c t a = +25c t a = ?40c lpen = 0 lpen = 1 ip1db gain 09335-004 figure 4. conversion gain and input p1db vs. lo frequency 20 22 24 26 28 30 32 34 36 38 40 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 input ip3 (dbm) lo frequency (mhz) t a = +85c t a = +25c t a = ?40c lpen = 0 lpen = 1 09335-005 figure 5. input ip3 vs. lo frequency ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 iq gain mism a tch (db) lo frequency (mhz) t a = +85c t a = +25c t a = ?40c lpen = 0 lpen = 1 09335-006 figure 6. iq gain mismatch vs. lo frequency 50 55 60 65 70 75 80 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 input ip2 (dbm) lo frequency (mhz) lpen = 1 lpen = 0 t a = +85c t a = +25c t a = ?40c i channel q channel 09335-007 figure 7. input ip2 vs. lo frequency 5 6 7 8 9 10 11 12 13 14 15 16 17 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 noise figure (db) lo frequency (mhz) t a = +85c t a = +25c t a = ?40c lpen = 0 lpen = 1 09335-008 figure 8. noise figure vs. lo frequency ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 iq quad r a ture phase error (degrees) lo frequency (mhz) t a = +85c t a = +25c t a = ?40c lpen = 0 lpen = 1 0 9335-009 figure 9. iq quadrature phase error vs. lo frequency adrf6806 data sheet rev. b | page 10 of 36 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ? 50 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 lo-to-rf feedthrough (dbm) lo frequency (mhz) lpen = 0 lpen = 1 0 9335-010 figure 10. lo-to-rf feedthrough vs. lo frequency, lo output turned off ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 lo-to-bb feedthrough (dbv rms) lo frequency (mhz) lpen = 0 lpen = 1 09335-011 figure 11. lo-to-bb feedthrough vs. lo frequency, lo output turned off ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ? 30 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 rf-to-bb feedthrough (dbc) rf frequency (mhz) lpen = 0 lpen = 1 09335-012 figure 12. rf-to-bb feedthrough vs. rf frequency ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 1 10 100 400 normalized baseband frequency response (db) baseband frequenc y (mhz) lpen = 0 lpen = 1 09335-013 figure 13. normalized bb frequency response 0 10 20 30 40 50 60 70 80 5 101520253035404550 input p1db (dbm), input ip2 (dbm), and input ip3 (dbm) baseband frequency (mhz) ip1db iip3 iip2 lpen = 0 lpen = 1 lpen = 0 lpen = 1 lpen = 0 lpen = 1 t a = +85c t a = +25c t a = ?40c i channel q channel 09335-014 figure 14. input p1db, input ip2, and input ip3 vs. bb frequency 8 10 12 14 16 18 20 22 24 26 28 30 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 noise figure (db) input blocker power (dbm) lpen = 0 lpen = 1 0 9335-015 figure 15. noise figure vs. input blocker level, f lo = 140 mhz (rf blocker 5 mhz offset) data sheet adrf6806 rev. b | page 11 of 36 ?30 ?28 ?26 ?24 ?22 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 rf return loss (db) rf frequency (mhz) 09335-016 figure 16. rf input return loss vs. rf frequency, measured through adtl2-18 2-to-1 input balun ?30 ?28 ?26 ?24 ?22 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 lo output return loss (db) lo output frequency (mhz) 09335-017 figure 17. lo output return loss vs. lo output frequency, lo output enabled (350 mhz to 1050 mhz) 60 85 110 135 160 185 210 235 260 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 current (ma) lo frequency (mhz) 3.3v supply 5v supply t a = +85c t a = +25c t a = ?40c lpen = 0 lpen = 1 09335-018 figure 18. 5 v and 3.3 v supply currents vs. lo frequency, lo output disabled 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 ?40 ?20 0 20 40 60 80 vpt a t voltage (v) temperature (c) lpen = 0 lpen = 1 09335-019 figure 19. vptat vs. temperature 0.5 1.0 1.5 2.0 2.5 3.0 3.5 350 370 390 410 430 450 470 490 510 vtune voltage (v) lo frequency (mhz) t a = +85c t a = +25c t a = ?40c 09335-020 figure 20. vtune vs. lo frequency adrf6806 data sheet rev. b | page 12 of 36 synthesizer/pll v s1 = 5 v, v s2 = 3.3 v, see the register structure section for recommended settings used. external loop filter bandwidth of ~67 khz, f ref = f pfd = 26 mhz, measured at bb output, f bb = 50 mhz, unless otherwise noted. ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ? 80 1k 10k 100k 1m 10m phase noise (dbc/hz) offset frequency (hz) 2.5khz loop filter 67khz loop filter t= \ t a = +85c t a = +25c t a = ?40c 09335-021 figure 21. phase noise vs. offset frequency, f lo = 140 mhz ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ? 70 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 pll reference spurs (dbc) lo frequency (mhz) 1 pfd frequency 3 pfd frequency 0.5 pfd frequency t a = +85c t a = +25c t a = ?40c 09335-022 figure 22. pll reference spurs vs. lo frequency ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ? 70 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525 pll reference spurs (dbc) lo frequency (mhz) 2 pfd frequency 4 pfd frequency t a = +85c t a = +25c t a = ?40c 09335-123 figure 23. pll reference spurs vs. lo frequency 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 50 100 150 200 250 300 350 400 450 500 integr a ted phase noise (rms) lo frequency (mhz) t a = +85c t a = +25c t a = ?40c 09335-024 figure 24. integrated phase noise vs. lo frequency (spurs omitted) ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ? 60 40 90 140 190 240 290 340 390 440 490 phase noise (dbc/hz) lo frequency (mhz) 5mhz offset 10khz offset 1khz offset 67khz loop filter bandwidth 2.5khz loop filter bandwidth t a = +85c t a = +25c t a = ?40c 09335-125 figure 25. phase noise vs. lo frequency (1 khz, 10 khz, and 5 mhz offsets) t a = +85c t a = +25c t a = ?40c ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ? 80 40 90 140 190 240 290 340 390 440 490 phase noise (dbc/hz) lo frequency (mhz) 1mhz offset 100khz offset 67khz loop filter bandwidth 2.5khz loop filter bandwidth 09335-126 figure 26. phase noise vs. lo frequency (100 khz and 1 mhz offsets) data sheet adrf6806 rev. b | page 13 of 36 complementary cumulative distribution functions (ccdf) v s1 = 5 v, v s2 = 3.3 v, f lo = 140 mhz, f bb = 4.5 mhz. 0 10 20 30 40 50 60 70 80 90 100 02468101214 cumul a tive distribution percentage (%) gain (db) and input p1db (dbm) ip1db t a = +85c t a = +25c t a = ?40c lpen = 0 lpen = 1 gain 09335-025 figure 27. gain and input p1db 0 10 20 30 40 50 60 70 80 90 100 20 22 24 26 28 30 32 34 cumul a tive distribution percentage (%) input ip3 (dbm) lpen = 0 lpen = 1 09335-026 t a = +85c t a = +25c t a = ?40c i channel q channel figure 28. input ip3 0 10 20 30 40 50 60 70 80 90 100 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 cumul a tive distribution percentage (%) iq gain mismatch (db) t a = +85c t a = +25c t a = ?40c lpen = 0 lpen = 1 09335-027 figure 29. iq gain mismatch 0 10 20 30 40 50 60 70 80 90 100 50 55 60 65 70 75 80 cumul a tive distribution percentage (%) input ip2 (dbm) lpen = 1 lpen = 0 t a = +85c t a = +25c t a = ?40c i channel q channel 09335-028 figure 30. input ip2 0 10 20 30 40 50 60 70 80 90 100 0 2 4 6 8 101214161820 cumul a tive distribution percentage (%) noise figure (db) t a = +85c t a = +25c t a = ?40c lpen = 0 lpen = 1 0 9335-029 figure 31. noise figure 0 10 20 30 40 50 60 70 80 90 100 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 cumul a tive distribution percentage (%) iq quadrature phase error (degrees) t a = +85c t a = +25c t a = ?40c lpen = 0 lpen = 1 09335-030 figure 32. iq quadrature phase error adrf6806 data sheet rev. b | page 14 of 36 circuit description the adrf6806 integrates a high performance iq demodulator with a state-of-the-art fractional-n pll. the pll also integrates a low noise vco. the spi port allows the user to control the fractional-n pll functions, the demodulator lo divider functions, and optimization functions, as well as allowing for an externally applied lo. the adrf6806 uses a high performance mixer core that results in an exceptional input ip3 and input p1db, with a very low output noise floor for excellent dynamic range. lo quadrature drive a signal at 2 the desired mixer lo frequency is delivered to a divide-by-2 quadrature phase splitter followed by limiting amplifiers which then drive the i and q mixers, respectively. v-to-i converter the differential rf input signal is applied to a v-to-i converter that converts the differential input voltage to output currents. the v-to-i converter provides a differential 100 input impedance. the v-to-i bias current can be reduced by putting the device in low power mode (setting lpen = 1 by setting register 5, db5 = 1). generally with lpen = 1, input ip3 and input p1db degrade, but the noise figure is slightly better. overall, the dynamic range is reduced by setting lpen = 1. mixers the adrf6806 has two double-bal anced mixers: one for the in- phase channel (i channel) and one for the quadrature channel (q channel). these mixers are based on the gilbert cell design of four cross-connected transistors. the output currents from the two mixers are summed together in the resistive loads that then feed into the subsequent emitter follower buffers. when the part is put into its low power mode (lpen = 1), the mixer core load resistors are increased, which does increase the gain by roughly 3 db; however, as previously stated in the v-to-i converter section, the overall dynamic range does decrease slightly. emitter follower buffers the output emitter followers drive the differential i and q signals off chip. the output impedance is set by on-chip 14 series resistors that yield a 28 differential output impedance for each baseband port. the fixed output impedance forms a voltage divider with the load impedance that reduces the effective gain. for example, a 500 differential load has ~0.5 db lower effective gain than a high (10 k) differential load impedance. the common-mode dc output levels of the emitter follower outputs are set by the voltage applied to the vocm pin. the vocm pin must be driven with a voltage (typically 1.65 v) for the emitter follower buffers to function. if the vocm pin is left open, the emitter follower outputs do not bias up properly. bias circuitry there are several band gap reference circuits and two low droput regulators (ldos) in the adrf6806 that generate the reference currents and voltages used by different sections. one of the ldos is the 2.5v_ldo, which is always active and provides the 2.5 v supply rail used by the internal digital logic blocks. the 2.5v_ldo output is connected to the decl2 pin (pin 9) for the user to provide external decoupling. the other ldo is the vco_ldo, which acts as the positive supply rail for the internal vco. the vco_ldo output is connected to the decl1 pin (pin 40) for the user to provide external decoupling. the vco_ldo can be powered down by setting register 6, db18 = 0, which allows the user to save power when not using the vco. additionally, the bias current for the mixer v-to-i stage, which drives the mixer core, can be reduced by putting the device in low power mode (setting lpen = 1 by setting register 5, db5 = 1). register structure the adrf6806 provides access to its many programmable features through a 3-wire spi control interface that is used to program the seven internal registers. the minimum delay and hold times are shown in the timing diagram (see figure 2 ). the spi provides digital control of the internal pll/vco as well as several other features related to the demodulator core, on-chip referencing, and available system monitoring functions. the muxout pin provides a convenient, single-pin monitor output signal that can be used to deliver a pll lock-detect signal or an internal voltage proportional to the local junction temperature. note that internal calibration for the pll must run when the adrf6806 is initialized at a given frequency. this calibration is run automatically whenever register 0, register 1, or register 2 is programmed. because the other registers affect pll performance, register 0, register 1, and register 2 must always be programmed last. for ease of use, starting the initial programming with register 7 and then programming the registers in descending order ending with register 0 is recommended. once the pll and other settings are programmed, the user can change the pll frequency simply by programming register 0, register 1, or register 2 as necessary. data sheet adrf6806 rev. b | page 15 of 36 divide mode db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0000000000000dmid6id5id4id3id2id1id0c3(0)c2(0)c1(0) dm 0 1 id6 id5 id4 id3 id2 id1 id0 0010101 0010110 0010111 0011000 ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0111000 ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1110111 1111000 1111001 1111010 1111011 ... ... 119 120 (integer mode only) divide ratio 21 (integer mode only) 22 (integer mode only) 23 (integer mode only) 24 ... ... 56 (default) integer integer divide ratio control bits divide mode fractional (default) 121 (integer mode only) 122 (integer mode only) 123 (integer mode only) 09335-031 figure 33. integer divide control register (r0) register 0integer divide control with r0[2:0] set to 000, the on-chip integer divide control register is programmed as shown in figure 33 . the internal vco frequency (f vco ) equation is f vco = f pfd ( int + ( frac / mod )) 2 (1) where: f vco is the output frequency of the internal vco. int is the preset integer divide ratio value (21 to 123 for integer mode, 24 to 119 for fractional mode). mod is the preset fractional modulus (1 to 2047). frac is the preset fractional divider ratio value (0 to mod ? 1). the integer divide ratio sets the int value in equation 1. the int, frac, and mod values make it possible to generate output frequencies that are spaced by fractions of the pfd frequency. note that the demodulator lo frequency is given by f lo = f vco /m, where m is the programmed lo main divider (see table 5 ). divide mode divide mode determines whether fractional mode or integer mode is used. in integer mode, the vco output frequency, f vco , is calculated by f vco = f pfd ( int ) 2 (2) adrf6806 data sheet rev. b | page 16 of 36 register 1modulus divide control with r1[2:0] set to 001, the on-chip modulus divide control register is programmed as shown in figure 34 . the mod value is the preset fractional modulus ranging from 1 to 2047. modulus divide ratio db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 0 md10 md9 md8 md7 md6 md5 md4 md3 md2 md1 md0 c3(0) c2(0) c1(1) md10 md9 md8 md7 md6 md5 md4 md3 md2 md1 md0 0 0000000001 0 0000000010 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1000000000 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1111111111 modulus value ... ... 2047 control bits 1 1536 (default) 2 ... ... 09993-032 figure 34. modulus divide control register (r1) register 2fractional divide control with r2[2:0] set to 010, the on-chip fractional divide control register is programmed as shown in figure 35 . the frac value is the preset fractional modulus ranging from 0 to mod ? 1. fd10fd9fd8fd7fd6fd5fd4fd3fd2fd1fd0 0 0000000000 0 0000000001 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0 1100000000 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... fractional value must be less than modulus fractional value 0 1 ... ... 768 (default) ... ... adrf6806 data sheet rev. b | page 18 of 36 charge pump ref pdf phase offset polarity cp cntl src db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 rms2 rms1 rms0 rs1 rs0 cpm cpbd cpb4 cpb3 cpb2 cpb1 cpb0 cpp1 cpp0 cps cpc1 cpc0 pe1 pe0 pab1 pab0 c3(1) c2(0) c1(0) cpc1 cpc0 00 01 10 11 cps 0 1 cpp1 cpp0 00 01 10 11 cpb4 cpb3 cpb2 cpb1 cpb0 00000 00001 00110 01010 ... ... ... ... ... 11111 cpbd 0 1 cpm 0 1 rs1 rs0 00 01 10 11 rms2 rms1 rms0 000 001 010 011 100 101 110 111 10 22.5/i cp, mult (default) ... 31 22.5/i cp, mult pfd phase offset multiplier 0 22.5/i cp, mult 1 22.5/i cp, mult 6 22.5/i cp, mult (recommended) both on pump down pump up tristate (default) ouput mux source input ref path source pfd phase offset multiplier value charge pump current multiplier charge pump control pfd edge sensitivity control bits pfd anti- backlash delay pe0 0 1 reference path edge sensitivity falling edge (recommended) rising edge (default) pab1 pab0 00 01 10 11 pfd antibacklash delay 0ns (default, recommended) 0.5ns 0.75ns 0.9ns charge pump control buffered version of 0.5 reference input charge pump control source control based on state of db7/db8 (cp control) control from pfd (default) output mux source lock detect (default) vptat buffered version of reference input pfd phase offset polarity negative positive (default, recommended) charge pump current reference source internal (default) external 0.25 reference input charge pump current multiplier 1 2 (default, recommended) 3 4 input reference path source 2 reference input reference input (default) 0.5 reference input buffered version of 2 reference input tristate reserved (do not use) pe1 0 1 divider path edge sensitivity falling edge (recommended) rising edge (default) ... ... ... ... ... ... ... ... ... ... ... ... reserved (do not use) 09335-035 figure 37. charge pump, pfd, and reference path control register (r4) data sheet adrf6806 rev. b | page 19 of 36 register 5lo path an d demodulator control with r5[db5] = 1, the adrf6806 is in a lower power operating mode. the device is still fully functional in this lower power mode, but the mixer performance is shifted (see the typical performance characteristics section for details on performance differences). setting r5[db5] = 0 causes the adrf6806 mixer stage to run at a higher current, thereby achieving a higher iip3. register 5 also controls whether the loip and loin pins act as an input or output and whether the output driver is enabled as detailed in figure 38 . demod bias enable low power mode enable lo in/out ctrl lo output driver enable db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 dmbe db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 lpen lxl ldrv c3(1) c2(0) c1(1) ldrv 0 1 lxl 0 1 lpen 0 1 disabled enabled (default) lo output driver enable driver off (default) driver on dmbe 0 1 disable enable (default) demod bias enable lo in/out control lo output (default) lo input low power mode control bits 000 0 0 000 000 0 09335-036 figure 38. lo path and demodu lator control register (r5) adrf6806 data sheet rev. b | page 20 of 36 register 6vco control and enables with r6[2:0] set to 110, the vco control and enables register is programmed as shown in figure 39 . vco band selection is normally selected based on bandcal calibration; however, the vco band can be selected directly using register 6. the vco bs src determines whether the bandcal calibration determines the optimum vco tuning band or if the external spi interface is used to select the vco tuning band based on the value of the vco band select. the vco amplitude can be controlled through register 6. the vco amplitude setting can be controlled between 0 and 31 decimal, with a default value of 24. the internal vco can be disabled using register 6. the internal vco ldo can be disabled if an external clean 3.0 v supply is available. the internal charge pump can be disabled through register 6. normally, the charge pump is enabled. charge pump enable 3.3v switch enable vco enable vco switch vco bs csr vbsrc 0 1 vco en vco ldo enable vco amplitude vco band select charge pump enable vco band cal and sw source control band cal (default) vco sw 0 1 vco switch control from spi regular (default) band cal spi vco enable disable enable (default) db22 db21 db20 db19 db18 db17 db16 db15 db14 db1 3 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 control bits db23 cpen l3en vco en vco sw vc5 vc4 vc3 vc2 vc1 vc0 vbsrc vbs5 vbs4 vbs3 vbs2 vbs1 vbs0 c3(1) c2(1) c1(0) lven 0 1 lven vco ldo enable disable enable (default) 0 1 l3en 3.3v switch enable disable enable (default) 0 1 cpen disable enable (default) 0 1 000 vc5 vc4 vc3 vc2 vc1 00000 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 10111 ... 63 vco amplitude 0 ... ... 01100 24 (recommended) 01111 vc0 0 ... ... ... 1 0 1 47 vbs5 vbs4 vbs3 vbs2 vbs1 00000 ... ... ... ... ... ... ... ... ... ... vco band select from spi 0 ... ... 10000 32 (default) 11111 vbs0 0 ... ... 0 1 63 ... ... ... ... ... 00100 ... 0 ... 8 (default) 09335-037 figure 39. vco control and enables (r6) data sheet adrf6806 rev. b | page 21 of 36 register 7lo divider control register 7 controls the lo path main divider settings as well as the lo output path divider setting. table 5 indicates how to program this register to achieve various divider modes. divider select div a/b control output div control db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 divs1 db6 db5 db4 db3 db2 db1 db0 0 0 divab1 divab0 divs0 odiv1 odiv0 0 c3(1) c2(1) c1(1) divab1 0 0 2 (default) 3 divide ratio control bits divab0 0 1 1 1 4 (not valid for divb) 5 (not valid for divb) 0 1 divs1 0 0 div b only (default) div a followed by 2 divide ratio divs0 0 1 1 1 div a followed by 4 div a followed by 8 0 1 odiv1 0 0 4 (default) 4 divide ratio odiv0 0 1 1 1 6 8 0 1 00000 000 000 0 09335-038 figure 40. lo divider control register (r7) lo divider programming table 5. main divider (only divide ratios and combinations specified are guaranteed) divider cascade f lo (mhz) lo divider ratio f vco (mhz) divideby2 to divideby5 divideby2 divideby4 or divideby uadrature divideby2 register 7 db6 35 to 52.5 80 2800 to 4200 5 8 2 11 11 43.75 to 65.62 64 2800 to 4200 4 8 2 10 11 58.33 to 87.5 48 2800 to 4200 3 8 2 01 11 70 to 105 40 2800 to 4200 5 4 2 11 10 87.5 to 131.25 32 2800 to 4200 4 4 2 10 10 116.7 to 175 24 2800 to 4200 3 4 2 01 10 140 to 210 20 2800 to 4200 5 2 2 11 01 175 to 262.5 16 2800 to 4200 4 2 2 10 01 233.3 to 350 12 2800 to 4200 3 2 2 01 01 350 to 525 8 2800 to 4200 2 2 2 00 01 table 6. output divider f lo output (mhz) output divider ratio f vco (mhz) register 7db54 350 to 525 8 2800 to 4200 11 466.67 to 700 6 2800 to 4200 10 700 to 1050 4 2800 to 4200 01 programming example for example, internal lo frequency = 140 mhz. this can be accomplished with the vco/pll frequency at 2800 mhz and an lo divide ratio of 20. the choice of output divider ratio of 8 gives an ou tput frequency of 350 mhz. to achieve this combination, a binar y code of 11 01 11 should be programmed into db[9:4] of register 7. adrf6806 data sheet rev. b | page 22 of 36 applications information basic connections the basic circuit connections for a typical adrf6806 application are shown in figure 41 . supply connections the adrf6806 has several supply connections and on-board regulated reference voltages that should be bypassed to ground using low inductance bypass capacitors located in close proximity to the supply and reference pins of the adrf6806. specifically pin 1, pin 2, pin 9, pin 10, pin 17, pin 22, pin 23, pin 28, pin 29, pin 34, and pin 40 should be bypassed to ground using individual bypass capacitors. pin 40 is the decoupling pin for the on-board vco ldo, and for best phase noise performance, several bypass capacitors ranging from 100 pf to 10 f may help to improve phase noise performance. for additional details on bypassing the supply nodes, see the evaluation board schematic in figure 43 . synthesizer connections the adrf6806 includes an on-board vco and pll for lo synthesis. an external reference must be applied for the pll to operate. a 1 v p-p nominal external reference must be applied to pin 6 through an ac coupling capacitor. the reference is compared to an internally divided version of the vco output frequency to create a charge pump error current to control and lock the vco. the charge pump output current is filtered and converted to a control voltage through the external loop filter that is then applied to the vtune pin (pin 39). adisimpll? can be a helpful tool when designing the external charge pump loop filter. the typical kv of the vco, the charge pump output current magnitude, and pfd frequency should all be considered when designing the loop filter. the charge pump current magnitude can be set internally or with an external rset resistor connected to pin 5 and ground, along with the internal digital settings applied to the pll (see the register 4charge pump, pfd, and reference path control section for more details). 40 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 21 22 23 24 25 26 27 28 29 30 ibbn losel ibbp gnd vcclo lon lop decl1 vtune gnd rfin vocm gnd vccbb gnd gnd rfip gnd vccrf decl3 qbbn gnd clk data qbbp vcclo le gnd gnd gnd muxout gnd rset vcc1 gnd cpout vcc2 refin vcc1 decl2 adrf6806 +3.3v +3.3 v +5v rf input +5v +3.3v external reference monitor output r2 open +3.3v spi control bb q-output balun if q-output rf input balun bb i-output balun if i-output charge pump loop filter +1.65v +3.3v 09335-039 figure 41. basic connections data sheet adrf6806 rev. b | page 23 of 36 i/q output connections the adrf6806 has i and q baseband outputs. each output stage consists of emitter follower output transistors with a low differential impedance of 28 and can source up to 12 ma p-p differentially. a mini-circuits tcm9-1+ balun is used to trans- form a single-ended 50 load impedance into a nominal 450 differential impedance. rf input connections the adrf6806 uses a mini-circuits adtl2-18+ balun with a 2:1 impedance ratio to transform a single-ended 50 impedance into a differential 100 impedance. coupling capacitors whose impedance is small compared to 100 at the frequency of operation are used to isolate the dc bias points of the rf input stage. charge pump/vtune connections the adrf6806 uses a loop filter to create the vtune voltage for the internal vco. the loop filter in its simplest form is an integrating capacitor. it converts the current mode error signal coming out of the cpout pin into a voltage in which to control the vco via the vtune voltage. the stock filter on the evaluation board has a bandwidth of 67 khz. the loop filter contains five components, three capacitors, and two resistors. changing the values of these components changes the bandwidth of the loop filter. lo select interface the adrf6806 has the option of either monitoring a scaled version of the internally generated lo (losel pin driven high at 3.3 v) or providing an external lo source (losel pin driven low to ground, the ldrv bit in register 5 set low, and the lxl bit in register 5 set high). see the pin configuration and function descriptions section for full operation details. external lo interface the adrf6806 provides the option to use an external signal source for the lo into the iq demodulating mixer core. it is important to note that the applied lo signal is divided down by a divider (programmable to between 4 and 80) prior to the actual iq demodulating mixer core. the divider is determined by the register settings in the lo path and mixer control register (see the register 5lo path and demodulator control section). the lo input pins (pin 37 and pin 38) present a broadband differential 50 input impedance. the lop and lon input pins must be ac-coupled. this is achieved on the evaluation board via a mini-circuits tc1-1-13+ balun with a 1:1 impedance ratio. when not in use, the lop and lon pins can be left unconnected. setting the frequency of the pll the frequency of the vco/pll, once locked, is governed by the values programmed into the pll registers, as follows: f pll = f pfd 2 ( int + frac / mod ) where: f pll is the frequency at the vco when the loop is locked. f pfd is the frequency at the input of the phase frequency detector. int is the integer divide ratio programmed into register 0. mod is the modulus divide ratio programmed into register 1. frac is the fractional value programmed into register 2. the practical lower limit of the reference input frequency is determined by the combination of the desired f pll and the maximum programmable integer divide ratio of 119 and reference input frequency multiplier of 2. for a maximum f pll of 4200 mhz, f ref > ~ f pll /( f pfd 2 2), or 8.8 mhz. a lock detect signal is available as one of the selectable outputs through the muxout pin, with logic high signifying that the loop is locked. register programming because register 6 controls the powering of the vco and charge pump, it must be programmed once before programming the pll frequency (register 0, register 1, and register 2). the registers should be programm ed starting with the highest register (register 7) first and then sequentially down to register 0 last. when register 0, register 1, or register 2 is programmed, an internal vco calibration is initiated that must execute when the other registers are set. therefore, the order must be register 7, register 6, register 5, register 4, register 3, register 2, register 1, and then register 0. whenever register 0, register 1, or register 2 is written to, it initializes the vco calibration (even if the value in these registers does not change). after the device has been powered up and the registers configured for the desired mode of operation, only register 0, register 1, or register 2 must be programmed to change the lo frequency. if none of the register values is changing from their defaults, there is no need to program them. adrf6806 data sheet rev. b | page 24 of 36 evm measurements figure 42 shows that the adrf6806 exhibited excellent evm performance, with the evm being better than ?40 db over an rf input range of about +35 db for a 4 qam modulated signal at a 5 mhz symbol rate at a 0 hz if. the pulse shaping filters roll-off, or alpha, was set to 0.35. evm and was tested for both power modes: lower power mode disabled (lpen = 0) and low power mode enabled (lpen = 1). when low power mode was enabled, the evm was better at lower rf input signal levels due to less noise while running in low power mode. while in normal power mode (lpen = 0), the evm remained undegraded at higher rf input signal levels. evm is a measure used to quantify the performance of a digital radio transmitter or receiver. a signal received by a receiver has all constellation points at their ideal locations; however, various imperfections in the implementation (such as magnitude imbalance, noise floor, and phase imbalance) cause the actual constellation points to deviate from their ideal locations. in general, a demodulator exhibits three distinct evm limitations vs. received input signal power. as signal power increases, the distortion components increase. at large enough signal levels, where the distortion components due to the harmonic non- linearities in the device are falling in-band, evm degrades as signal levels increase. at medium signal levels, where the demodulator behaves in a linear manner and the signal is well above any notable noise contributions, the evm has a tendency to reach an optimal level determined dominantly by either quadrature accuracy and i/q gain match of the demodulator or the precision of the test equipment. as signal levels decrease, such that the noise is a major contribution, the evm performance vs. the signal level exhibits a decibel-for-decibel degradation with decreasing signal level. at lower signal levels, where noise proves to be the dominant limitation, the decibel evm proves to be directly proportional to the snr. ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 evm (db) rf input power (dbm) 09335-142 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 lpen = 0 lpen = 1 the basic test setup to test evm for the adrf6806 consisted of an agilent e4438c, which was used as a signal source. the 140 mhz modulated signal was driven single-ended into the rfin sma connector of the adrf6806 evaluation board. the iq baseband outputs were taken differentially into a pair of ad8130 difference amplifiers to convert the differential signals to single-ended. the output impedance driven by the adrf6806 was set to 450 differential. the single-ended i and q signals were then sampled by an agilent dso7104b oscilloscope. the agilent 89600 vsa software was used to calculate the evm of the signal. the signal source used for the reference input was a wenzel 100 mhz quartz oscillator set to an amplitude of 1 v p-p. the reference path was set to divide-by-four, resulting in a pfd frequency of 25 mhz. figure 42. evm measurements @ 140 mh z 16 qam; symbol rate = 5 mhz; bb if frequency of 5 mhz data sheet adrf6806 rev. b | page 25 of 36 evaluation board layout and thermal grounding an evaluation board is available for testing the adrf6806. the evaluation board schematic is shown in figure 43 . table 7 provides the component values and suggestions for modifying the component values for the various modes of operation. 40 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 21 22 23 24 25 26 27 28 29 30 ibbn losel ibbp gnd vcclo lon lop decl1 vtune gnd rfin vocm gnd vccbb gnd gnd rfip gnd vccrf decl3 qbbn gnd clk data data qbbp vcclo le gnd gnd gnd muxout gnd rset vcc1 gnd cpout vcc2 refin vcc1 decl2 adrf6806 vcc3 0.1f 100pf cp lo vcc_lo 10f decl3 100pf vcc_rf 1nf 1nf rfin 100pf vcc_bb 1000pf 1000pf c14 300pf c15 6.2nf r10 1.6k ? 9 r qout_se 0.1f 100pf vcc_lo refin refout 2p5v 0 ? 0 ? 0 ? 0 ? 0 ? vcc2 net name test point 49.9 ? 1nf r47 r48 r44 r43 r42 c29 0.1f t3 p3 t4 t1 r2 r8 c12 c11 c10 100pf c9 0.1f r7 c36 100pf c26 c24 r28 c25 r6 0 ? c8 100pf c7 0.1f c6 c5 r37 r38 5.6k ? c13 62pf r1 r12 r11 c1 100pf c2 0.1f vco_ldo c31 r26 r16 r18 c16 100pf c17 0.1f c27 10f 2p5v_ldo r17 c18 100pf c19 0.1f 10f c3 open r50 open clk c32 open r51 open c33 open r52 open c34 le gnd gnd1 gnd2 c21 c20 r24 c22 c23 r25 c38 c39 vcc_rf vcc_bb r29 r32 vcc c28 10f open open open c4 10f r15 r13 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? r27 r34 10f c37 r14 vcc3 3.3v_force 3.3v_sense r21 r22 2 4 5 1 3 qbbp qbbn r23 open open c40 4 61 3 iout_se r41 r40 r39 c30 0.1f 0.1f 0.1f 0.1f t2 0 ? r4 2 4 51 3 ibbp ibbn r3 open open r46 open r45 r56 r55 10k ? 10k ? vcc s1 13 4 5 2 c35 10f open r49 3p3v1 3p3v2 vcc_lo1 dig_gnd vcc_bb1 vocm r62 4.99k ? 4.99k ? r63 3p3v_force vocm p1 vcc_rf r31 0 ? 3p3v_force vcc_lo vcc p2 0 ? 0 ? 0 ? 0 ? 0 ? r5 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 0 ? 09993-042 open data clk le jp1 sma input/output figure 43. evaluation board schematic adrf6806 data sheet rev. b | page 26 of 36 56 55 54 53 52 51 50 49 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 35 36 37 38 39 40 41 42 pd7_fd15 pd4_fd12 pd6_fd14 pd5_fd13 gnd clkout gnd vcc pa5_fifoard1 pa2_sloe reset_n pa3_wu2 pa4_fifoard0 pa6_pktend pa7_flagd_scls_n gnd vcc sda pb4_fd4 pb3_fd3 pb0_fd0 scl pb1_fd1 pb2_fd2 dplus xtalout xtalin rdy1_slwr avcc avcc agnd rdy0_slrd cy7c68013a-56ltxc u4 le 9 dminus 10 agnd 11 vcc 12 gnd 13 ifclk 14 reserved 23 pb5_fd5 24 pb6_fd6 27 vcc 25 pb7_fd7 26 gnd 28 gnd 29 30 31 32 33 34 ctl1_flagb pa1_int1_n ctl0_flaga ctl2_flagc vcc pa0_int0_n 48 47 46 45 44 43 wakeup vcc pd0_fd8 pd1_fd9 pd3_fd11 pd2_fd10 clk data 3v3_usb 3v3_usb 3v3_usb c48 10pf c49 0.1f 3v3_usb 3v3_usb r61 2k? cr2 3v3_usb r64 100k? c58 0.1f c45 0.1f r62 100k ? 3v3_usb y1 24mhz 3 4 2 1 c54 22pf c51 22pf 1 2 3 4 5 g1 g2 g3 g4 5v_usb p5 a0 a1 a2 gnd sda scl wc_n vcc 3v3_usb 3v3_usb 24lc64-i_sn u2 adp3334 u3 1 8 2 3 4 7 6 5 out1 out2 fb nc in2 in1 sd gnd 1 8 2 3 4 7 6 5 c47 1.0f r65 2k ? cr1 5v_usb r69 78.7k ? c50 1000pf r70 140k ? c52 1.0f 3v3_usb dgnd c53 0.1f c42 0.1f c55 0.1f c41 0.1f c43 0.1f c44 0.1f c46 0.1f 3v3_usb r60 2k ? r19 2k ? c56 10pf c57 0.1f 09335-046 figure 44. data sheet adrf6806 rev. b | page 27 of 36 the package for the adrf6806 features an exposed paddle on the underside that should be well soldered to an exposed opening in the solder mask on the evaluation board. figure 45 illustrates the dimensions used in the layout of the adrf6806 footprint on the adrf6806 evaluation board (1 mil. = 0.0254 mm). note the use of nine via holes on the exposed paddle. these ground vias should be connected to all other ground layers on the evaluation board to maximize heat dissipation from the device package. under these conditions, the thermal impedance of the adrf6806 was measured to be approximately 30c/w in still air. 0.168 0.232 0.177 0.035 0.050 0.012 0.025 0.020 0 9335-043 figure 45. evaluation board layout dimensions for the adrf6806 package 09335-044 figure 46. adrf6806 evaluation board top layer 0 9335-045 figure 47. adrf6806 evaluation board bottom layer adrf6806 data sheet rev. b | page 28 of 36 table 7. evaluation board configuration options component function default condition vcc, vcc2, vcc_ldo, vcc_lo, vcc_lo1, vcc_rf, vcc_bb1, 3p3v1, 3p3v2, 3p3v_force, 2p5v, clk, data, le, cp, dig_gnd, gnd, gnd1, gnd2 power supply, ground and other test points. connect a 5 v supply to vcc. connect a 3.3 v supply to 3p3v_force. vcc, vcc2, vcc_lo, vcc_rf, vcc_bb1, vcc_lo1, vco_ldo, 3p3v1, 3p3v2, 2p5v = components corporation tp-104-01-02, cp, le, clk, data, 3p3v_force = components corporation tp-104-01-06, gnd, gnd1, gnd2, dig_gnd = components corporation tp-104-01-00 r1, r6, r7, r8, r13, r14, r15, r17, r18, r24, r25, r27, r28, r29, r31, r32, r34, r36, r49 power supply decoupling. shorts or power supply decoupling resistors. r1, r6, r7, r8 = 0 (0402), r13, r14, r15, r17 = 0 (0402), r18, r24, r25, r27 = 0 (0402), r28, r29, r31, r32 = 0 (0402), r34, r36 = 0 (0402), r49 = open (0402) c1, c2, c3, c4, c7, c8, c9, c10, c11, c12, c16, c17, c18, c19, c20, c21, c22, c23, c24, c25, c26, c27, c28, c35, c36, c37, c40 the capacitors provide the required decoupling of the supply-related pins. c1, c8, c10, c12 = 100 pf (0402), c16, c18, c21, c22 = 100 pf (0402), c24, c26 = 100 pf (0402), c2, c7, c9, c11 = 0.1 f (0402), c17, c19, c20, c23 = 0.1 f (0402), c25, c40 = 0.1 f (0402), c3, c4, c27, c35 = 10 f (0603), c36, c37 = 10 f (0603), c28 = 10 f (3216) t1, c5, c6 external lo path. the t1 transformer provides single-ended-to-differential conversion. c5 and c6 provide the necessary ac coupling. c5, c6 = 1 nf (0603), t1 = tc1-1-13+ mini-circuits r16, r26, r58, c31 refin input path. r26 pr ovides a broadband 50 termination followed by c31, which provides the ac coupling into refin. r16 provides an external connectivity to the muxout feature described in register 4. r58 provides option for connectivity to the p1-6 line of a 9-pin d-sub connector for dc measurements. r26 = 49.9 (0402), r16 = 0 (0402), r58 = open (0402), c31 = 1 nf (0603) r2, r9, r10, r11, r12, r37, r38, r59, c14, c15, c13 loop filter component options. a variety of loop filter topologies is supported using component placements c13, c14, c15, r9, and r10. r38 and r59 provide connectivity options to numerous test points for engineering evaluation purposes. r2 provides resistor progra mmability of the charge pump current (see register 4 description). r37 connects the charge pump output to the loop filter. r12 references the loop filter to the vco_ldo. r12, r37, r38 = 0 (0402), r59 = open (0402), r9 = 5.6 k (0402), r10 = 1.6 k (0402), r2, r11 = open (0402), c13 = 62pf (0402), c14 = 300pf (0402), c15 = 6.2nf (1206) r3, r4, r5, r21, r22, r23, r39, r40, r41, r42, r43, r44, r45, r46, r47, r48, c29, c30, t2, t3, p2, p3 if i/q output paths. the t2 and t3 baluns provide a 9:1 impedance transformation; therefore, with a 50 load on the single-ended iout/qout side, the center tap side of the balun presents a differential 450 to the adrf6806. the center taps of the baluns are ac grounded through c29 and c30. the baluns create a differential-to-single-ended conversion for ease of testing and use, but an option to have straight differential outputs is ac hieved via populating r3, r39, r23, and r42 with 0 resistors and removing r4, r5, r21, and r22. p2 and p3 are differential measurement test points (not to be used as jumpers). r4, r5, r21, r22, = 0 (0402), r40, r43, r45, r46 = 0 (0402), r47, r48 = 0 (0402), r3, r23, r39, r41, r42, r44 = open (0402), c29, c30, = 0.1 f (0402), t2, t3 = tcm9-1+ mini-circuits, p2, p3 = samtec ssw-102-01-g-s c38, c39, t4 rf input interface. t4 provides the single-ended- to-differential conversion required to drive rfip and rfin. t4 provides a 2:1 impedance transformation. a single-ended 50 load on the rfin sma connector transforms to a differential 100 presented across the rfip (pin 25) and rfin (pin 26) pins. c38 and c39 are ac coupling capacitors. c38, c39 = 1000 pf (0402), t4 = adtl2-18+ mini-circuits data sheet adrf6806 rev. b | page 29 of 36 component function default condition r50, r51, r52, c32, c33, c34 serial port interface. optional rc filters can be installed on the clk, data, and le lines to filter the pc signals through r50 to r52 and c32 to c34. clk, data, and le signals can be observed via test points for debug purposes. r50, r51, r52 = open (0402), c32, c33, c34 = open (0402) r33, r55, r56, s1 lo select interface. the losel pin, in combination with the ldrv and lxl bits in register 5, controls whether the lop and lon pins operate as inputs or outputs. a detailed description of how the losel pin, ldrv bit, and the lxl bit work together to control the lop and lon pins is found in table 4 under the losel pin description. using the s1 switch, the user can pull losel to a logic high (v cc /2) or a logic low (ground). resistors r55 and r56 form a resistor divider to provide a logic high of v cc /2. lo select can also be controlled through pin 9 of j1. the 0 jumper, r33, must be installed to control losel via j1. r33 = 0 (0402), r55, r56 = 10 k (0402), s1 = samtec tsw-103-08-g-s j1, p1, r62, r63 engineering test points and external control. j1 is a 10-pin connector connected to various important points on the evaluation board that the user can measure or force voltages upon. r62 and r63 form a voltage divider to force a voltage of 1.65 v on vocm. note that jumper p5 must be connected to drive vocm with the resistor divider. r62 = r63 = 4.99 k (0402), p1 = samtec ssw-102-01-g-s, j1 = molex connector corp. 10-89-7102 u2, u3, u4, p5 cypress microcontroller, eeprom, and ldo. u2 = microchip technology inc. micro24lc64, u3 = analog devices, inc., adp3334acpz, u4 = cypress semiconductor cy7c68013a-56ltxc, p5 = mini usb connector c41, c42, c43, c44, c46, c53, c55 3.3 v supply decoupling. several capacitors are used for decoupling the 3.3 v supply. c41, c42, c43, c44, c46, c53, c55 = 0.1 f (0402) c45, c47, c48, c49, c50, c52, c56, c57, c58, r19, r60, r61, r62, r64, r65, r69, r70, cr1, cr2 usb microcontroller section components c47, c52 = 1 f (0402), c48, c56 = 10 pf (0402), c45, c49, c57, c58 = 0.1 f (0402), c50 = 1000 pf (0402), r19, r60, r61 = 2 k (0402), r62, r64 = 100 k (0402), r65 = 2 k (0402), r69 = 78.7 k (0402), r70 = 140 k (0402), cr1 = rohm semiconductor sml-21omtt86, cr2 = rohm semiconductor sml-21omtt86 y1, c51, c54 crystal oscillator (24 mhz) and components. y1 = ndk nx3225sa-24mhz, c51, c54 = 22 pf (0402) adrf6806 data sheet rev. b | page 30 of 36 adrf6806 software the adrf6806 evaluation board can be controlled from pcs using a usb adapter board, which is also available from analog devices, inc.. the usb adapter evaluation documentation and ordering information can be found on the eval-adf4xxxz-usb product page. the basic user interfaces are shown in figure 48 and figure 49 . the software allows the user to configure the adrf6806 for various modes of operation. the internal synthesizer is controlled by clicking on any of the numeric values listed in rf section . attempting to program ref input frequency , pfd frequency , vco frequency (2lo) , lo frequency , or other values in rf section launches the synth form window shown in figure 49 . using synth form , the user can specify values for local oscillator frequency (mhz) and external reference frequency (mhz) . the user can also enable the lo output buffer and divider options from this menu. after setting the desired values, it is important to click upload all registers for the new setting to take effect. 09993-148 figure 48. evaluation board software main window data sheet adrf6806 rev. b | page 31 of 36 09993-149 figure 49. evaluation board software synth form window adrf6806 data sheet rev. b | page 32 of 36 characterization setups figure 50 to figure 52 show the general characterization bench setups used extensively for the adrf6806. the setup shown in figure 50 was used to do the bulk of the testing. an automated agilent vee program was used to control the equipment over the ieee bus. this setup was used to measure gain, input p1db, output p1db, input ip2, input ip3, iq gain mismatch, iq quadrature accuracy, and supply current. the evaluation board was used to perform the characterization with a mini-circuits tcm9-1+ balun on each of the i and q outputs. when using the tcm9-1+ balun below 5 mhz (the specified 1 db low frequency corner of the balun), distortion performance degrades; however, this is not the adrf6806 degrading, merely the low frequency corner of the balun introducing distortion effects. through this balun, the 9-to-1 impedance transformation effectively presented a 450 differential load at each of the i and q channels. the use of the broadband mini-circuits adtl2-18+ balun on the input provided a differential balanced rf input. the losses of both the input and output baluns were de-embedded from all measurements. to do phase noise and reference spur measurements, the setup shown in figure 52 was used. phase noise was measured at the baseband output (i or q) at a baseband carrier frequency of 50 mhz. the baseband carrier of 50 mhz was chosen to allow phase noise measurements to be taken at frequencies of up to 20 mhz offset from the carrier. the noise figure was measured using the setup shown in figure 51 at a baseband frequency of 10 mhz. data sheet adrf6806 rev. b | page 33 of 36 r&s smt03 signal generator r&s smt03 signal generator agilent e3631a power supply mini circuits zhl-42w amplifier (supplied with +15vdc for operation) agilent 11636a power divider (used as combiner) ref rf2 rf1 rf switch matrix adrf6806 evaluation board rf 6db 3db 3db 3db 3db 3db 6db i ch agilent 34980a multifunction switch (with 34950 and 2 34921 modules) 10-pin connection (+5v vpos1, +3.3v vpos2, dc measure) 9-pin d-sub connection (vco and pll programming) rf ie ieee ieee agilent dmm (for i 3.3v vp2 meas.) r&s sma100 signal generator agilent mxa spectrum analyzer hp 8508a vector voltmeter q ch agilent dmm (for i-5v vp1 meas.) ref ieee ieee ieee ieee ieee ieee ieee ieee ieee ieee ch a ch b 6db 09335-048 ieee figure 50. general characterization setup adrf6806 data sheet rev. b | page 34 of 36 agilent e3631a power supply ref rf switch matrix adrf6806 evaluation board rf 6db 3db 6db i ch 10-pin connection (+5v vpos1, +3.3v vpos2, dc measure) 9-pin d-sub connection (vco and pll programming) ie ieee agilent dmm (for i 3.3v vp2 meas.) q ch agilent dmm (for i-5v vp1 meas.) ref e ieee ieee ieee ieee ieee ieee ieee 6db rf1 agilent n8974a noise figure analyzer agilent 346b noisesource agilent 8665b low noise syn signal generator 10mhz low-pass filter rf 3db 09335-049 ieee agilent 34980a multifunction switch (with 34950 and 2 34921 modules) figure 51. noise figure characterization setup data sheet adrf6806 rev. b | page 35 of 36 agilent e3631a power supply ref rf switch matrix adrf6806 evaluation board rf 6db 3db 6db i ch 10-pin connection (+5v vpos1, +3.3v vpos2, dc measure) 9-pin d-sub connection (vco and pll programming) ie ieee agilent dmm (for i 3.3v vp2 meas.) q ch agilent dmm (for i-5v vp1 meas.) ref e ieee ieee ieee ieee ieee ieee ieee ieee ieee 6db rf1 rf 3db agilent mxa spectrum analyzer agilent e5052 signal source analyzer r&s sma100 signal generator r&s sma100 signal generator 100mhz low-pass filter 09335-050 ieee agilent 34980a multifunction switch (with 34950 and 2 34921 modules) figure 52. phase noise characterization setup adrf6806 data sheet rev. b | page 36 of 36 outline dimensions compliant to jedec standards mo-220-vjjd-2 122107-a 1 40 10 11 29 28 20 19 4.45 4.30 sq 4.15 top view 6.00 bsc sq 5.75 bsc sq coplanarity 0.08 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bot tom view) pin 1 indicator 0.30 0.23 0.18 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom s eating plane for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 53. 40-lead lead frame chip scale package [lfcsp_vq] 6 mm 6 mm body, very thin quad (cp-40-4) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ordering quantity adrf6806acpz-r7 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-4 750 ADRF6806-EVALZ evaluation board 1 z = rohs compliant part. ?2010C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09335-0-3/12(b) |
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